! Directives

- Expressions and operators, Symbolic capabilities

# Directives

$ Symbolic capabilities, Macros

% Symbolic capabilities, Directives

* Symbolic capabilities, Expressions and operators

+ Expressions and operators, Symbolic capabilities

. Symbolic capabilities

/ Expressions and operators

/= Expressions and operators

< Symbolic capabilities

= Symbolic capabilities

> Symbolic capabilities

>= Expressions and operators

? Expressions and operators

@ Symbolic capabilities

[ Conditional assembly 1, 2

] Conditional assembly 1, 2

^ Directives

__RelocCode Writing relocatable modules

| Conditional assembly 1, 2

Abort mode see ABT mode

aborts The ARM CPU 1, 2

see also The ARM CPU data aborts and prefetch aborts

ABS ARM assembly language 1, 2, Floating point instructions 1, 2, Support for AAsm source

ABS$$BLOCK Support for AAsm source

ABT mode The ARM CPU 1, 2, 3, 4

ACS Floating point instructions 1, 2

ADC CPU instruction set 1, 2

ADD CPU instruction set 1, 2, 3

address bus The ARM CPU 1, 2, 3, 4

address exceptions The ARM CPU 1, 2, 3, 4, 5, CPU instruction set 1, 2, Exception handling, Warnings on the use of ARM assembler 1, 2

addressing CPU instruction set 1, 2, 3, 4

ADF Floating point instructions 1, 2

ADR CPU instruction set

ADRL CPU instruction set

ALIGN ARM assembly language, Directives

ALU The ARM CPU 1, 2, CPU instruction set

an see registers (names)

AND CPU instruction set 1, 2, Symbolic capabilities

AOF Support for AAsm source

AOUT Support for AAsm source

APCS ObjAsm 1, 2, Symbolic capabilities, Interworking assembler with C 1, 2

AREA ARM assembly language, Writing relocatable modules, Support for AAsm source

AREAs ARM assembly language 1, 2, Directives

|$$$$$$$| ARM assembly language

|C$$code| ARM assembly language

attributes ObjAsm, ARM assembly language

code ObjAsm, ARM assembly language

data ARM assembly language

relocatable address constants ARM assembly language

arithmetic logic unit The ARM CPUsee ALU

Arithmetic Shift Left CPU instruction setsee ASL

Arithmetic Shift Right CPU instruction setsee ASR

ARM

configuration ObjAsm

core The ARM CPU

CPU The ARM CPU 1, 2

versions Introduction, ObjAsm, The ARM CPU 1, 2, Exception handling

ARM Procedure Call Standard ObjAsmsee APCS

ARM2 The ARM CPU 1, 2, 3, CPU instruction set 1, 2

ARM250 CPU instruction set

ARM3 The ARM CPU 1, 2, 3, CPU instruction set 1, 2

ARM6 ObjAsm, The ARM CPU 1, 2, CPU instruction set, Exception handling, Changes to the assembler

ARM7 ObjAsm, The ARM CPU 1, 2, CPU instruction set, Exception handling, Changes to the assembler

ARM7M ObjAsm, The ARM CPU, CPU instruction set, Changes to the assembler, Example assembler fragments

ASL CPU instruction set

AsmHello example ObjAsm

AsmModule example Writing relocatable modules

ASN Floating point instructions 1, 2

ASR CPU instruction set

assembly language Macros

examples Example assembler fragments 1, 2

ASSERT Directives

ATN Floating point instructions 1, 2

barrel shifter The ARM CPU 1, 2, CPU instruction set 1, 2

carry in CPU instruction set

carry out CPU instruction set

BASE Expressions and operators

BASED Rn ARM assembly language

bibliography Introduction

BIC CPU instruction set 1, 2

BL CPU instruction set 1, 2

booleans ARM assembly languagesee constants

buttons ObjAsmsee application (button name)

C language Interworking assembler with C 1, 2

static variables Interworking assembler with C

cacheing ObjAsmsee ObjAsm (cacheing)

Carry flag The ARM CPUsee C flag

case sensitivity ObjAsm, ARM assembly language, Symbolic capabilities, Changes to the assembler

CC Expressions and operators

CDP CPU instruction set 1, 2, Warnings on the use of ARM assembler

changes Changes to the assembler

CHR Expressions and operators

C language

static variables Interworking assembler with C

CMF Floating point instructions 1, 2

CMFE Floating point instructions 1, 2

CMN The ARM CPU, CPU instruction set 1, 2, 3, Warnings on the use of ARM assembler

CMNP see CMN

CMP The ARM CPU, CPU instruction set 1, 2, 3, Warnings on the use of ARM assembler

CMPP see CMP

CN CPU instruction set, Symbolic capabilities

CNF Floating point instructions 1, 2

CNFE Floating point instructions 1, 2

CODE ARM assembly language

COMDEF ARM assembly language

comments Symbolic capabilities

COMMON ARM assembly language

condition codes The ARM CPU 1, 2, CPU instruction set 1, 2, Example assembler fragments 1, 2, 3, 4, Warnings on the use of ARM assembler 1, 2

conditional assembly ObjAsm, Conditional assembly 1, 2

CONFIG ObjAsm 1, 2, Symbolic capabilities

configurations The ARM CPU 1, 2, 3, Exception handling 1, 2

constants Symbolic capabilities 1, 2

immediate CPU instruction set

conventions Introduction

coprocessors The ARM CPU 1, 2, CPU instruction set 1, 2, 3, Symbolic capabilities

floating point CPU instruction set

COS Floating point instructions 1, 2

CP CPU instruction set, Symbolic capabilities

CPSR The ARM CPU 1, 2, 3, 4, 5, CPU instruction set 1, 2, 3

CStatics example Interworking assembler with C 1, 2

C stringsDirectives

current program status register see CPSR

data aborts The ARM CPU 1, 2, 3, 4, CPU instruction set 1, 2, 3, 4, 5, Exception handling

data bus The ARM CPU 1, 2

data types The ARM CPU

DCB Directives

DCD Directives

DCFD Floating point instructions, Directives

DCFS Floating point instructions, Directives

DCW Directives

DDT ObjAsm

debugging ObjAsm

machine level ObjAsm

source level ObjAsm

tables ObjAsm

DEF Expressions and operators

dependency lists ObjAsm

dialogue boxes see application (dialogue box name)

directives ARM assembly language, Symbolic capabilities, Directives 1, 2, Support for AAsm source

see also directive name

DVF Floating point instructions 1, 2

END ARM assembly language, Directives

ENDIAN ObjAsm, Symbolic capabilities

ENDIF Conditional assembly 1, 2

ENTRY Directives, Writing relocatable modules, Support for AAsm source

EOR CPU instruction set, Symbolic capabilities

EQU Symbolic capabilities

errors ObjAsm 1, 2, 3, Directives, Error messages 1, 2

browser ObjAsm 1, 2

escapes ObjAsm

exception vectors The ARM CPUsee hardware vectors

exceptions The ARM CPU 1, 2, 3, 4, Exception handling 1, 2

priority system The ARM CPU

see also exception names The ARM CPU

EXP Floating point instructions 1, 2

EXPORT Directives, Error messages

expressions Expressions and operators 1, 2

Fast Interrupt mode The ARM CPUsee FIQ mode

FDV Floating point instructions 1, 2

FIQ The ARM CPU 1, 2, Exception handling 1, 2, 3

latency The ARM CPU

FIQ disable flag The ARM CPU 1, 2, 3, 4

FIQ mode The ARM CPU 1, 2, 3, 4, Exception handling

FIX Floating point instructions

flags The ARM CPUsee flag names

floating point Floating point instructions 1, 2, Directives, Writing relocatable modules

available systems Floating point instructions

C flag Floating point instructions 1, 2

denormalised numbers Floating point instructions

division by zero Floating point instructions

double extended precision Floating point instructions

expanded packed decimal Floating point instructions 1, 2

exponents Floating point instructions 1, 2

IEEE double precision Floating point instructions

IEEE single precision Floating point instructions

inexact results Floating point instructions

infinities Floating point instructions 1, 2, 3

invalid operations Floating point instructions

NaNs Floating point instructions 1, 2, 3, 4

number formats Floating point instructions 1, 2

number input Floating point instructions

overflow Floating point instructions

packed decimal Floating point instructions 1, 2

precision Floating point instructions

rounding Floating point instructions

store loading directives Floating point instructions

synchronous operation Floating point instructions

underflow Floating point instructions

writeback Floating point instructions

FLT Floating point instructions

FML Floating point instructions 1, 2

FN Floating point instructions, Symbolic capabilities

fp see registers (names)

FPREGARGS Directives

FRD Floating point instructions 1, 2

GET ObjAsm 1, 2, Directives 1, 2

see also exceptions

IF Conditional assembly 1, 2

image files ObjAsm 1, 2, 3

immediate constants CPU instruction setsee constants (immediate)

IMPORT Directives, Writing relocatable modules, Support for AAsm source

INCLUDE ObjAsm, Directives

include file searching ObjAsm

INDEX Expressions and operators

initialising memory Directivessee memory (initialising)

installation Introduction

instruction set The ARM CPU 1, 2

instructions

block data transfer The ARM CPU 1, 2, 3, 4, CPU instruction set 1, 2

branches The ARM CPU 1, 2, 3, CPU instruction set 1, 2

conversions CPU instruction set

coprocessor data operations CPU instruction set 1, 2

coprocessor data transfers CPU instruction set 1, 2

coprocessor register transfers CPU instruction set 1, 2

data processing The ARM CPU 1, 2, CPU instruction set 1, 2, 3, Warnings on the use of ARM assembler 1, 2

floating point coprocessor data operations Floating point instructions 1, 2

floating point coprocessor data transfer Floating point instructions 1, 2

floating point coprocessor multiple data transfer Floating point instructions 1, 2

floating point coprocessor register transfer Floating point instructions

floating point coprocessor status transfer Floating point instructions 1, 2

further CPU instruction set 1, 2

multiplies CPU instruction set 1, 2, 3, Warnings on the use of ARM assembler

PSR transfer The ARM CPU 1, 2, 3, CPU instruction set 1, 2

single data swap CPU instruction set 1, 2

single data transfer The ARM CPU 1, 2, ARM assembly language, CPU instruction set 1, 2, 3

software interrupt The ARM CPU 1, 2, 3, CPU instruction set 1, 2, 3, Writing relocatable modules

SWI The ARM CPU

timings CPU instruction set

undefined The ARM CPU 1, 2, 3, CPU instruction set 1, 2, 3, Floating point instructions, Warnings on the use of ARM assembler 1, 2, 3

Interrupt mode The ARM CPUsee IRQ mode

interrupts The ARM CPU

ip ObjAsmsee registers (names)

IRQ The ARM CPU, Exception handling

latency The ARM CPU

IRQ disable flag The ARM CPU 1, 2, 3, 4, 5, 6, 7, Exception handling

IRQ mode The ARM CPU 1, 2, 3, 4

local Expressions and operators

LAND Expressions and operators

layout of memory see memory (laying out)

LCL ARM assembly language, Symbolic capabilities, Macros

LDC CPU instruction set 1, 2, Warnings on the use of ARM assembler 1, 2, 3, 4

LDF Floating point instructions 1, 2, Warnings on the use of ARM assembler

LDM CPU instruction set 1, 2, Directives, Warnings on the use of ARM assembler 1, 2, 3, 4, 5, 6

LDR CPU instruction set 1, 2, 3, Warnings on the use of ARM assembler 1, 2, 3, 4

LDRB CPU instruction setsee LDR

LEADR Support for AAsm source

LEAF Directives

LEFT Expressions and operators

LEN Expressions and operators

LEOR Expressions and operators

LFM Floating point instructions 1, 2

LGN Floating point instructions 1, 2

libraries ObjAsm

Link Introduction, ObjAsm 1, 2, ARM assembly language

Debug ObjAsm

Module Writing relocatable modules

link register The ARM CPUsee LR

listings ObjAsm 1, 2, Macros

options Directives

literals CPU instruction set, Directives

floating point Floating point instructions

LNK ObjAsm

LNOT Expressions and operators

LOG Floating point instructions 1, 2

Logical Shift Left CPU instruction setsee LSL

Logical Shift Right CPU instruction setsee LSR

LOR Expressions and operators

LR The ARM CPU 1, 2, 3, CPU instruction set 1, 2, Exception handling, Writing relocatable modules

LSL CPU instruction set 1, 2

LSR CPU instruction set 1, 2

LTORG Floating point instructions, Directives

macros Conditional assembly, Macros 1, 2, Support for AAsm source

labels Symbolic capabilities

names ObjAsm

nesting Macros

parameters Macros 1, 2, 3

prototype statements Macros 1, 2

Make ObjAsm 1, 2, 3

MCR CPU instruction set 1, 2

memory

initialising Directives 1, 2

interface The ARM CPU

laying out Directives

reserving Directives

MEND Directives, Macros

menus see application (menu name)

MEXIT Macros

MLA CPU instruction set 1, 2, Warnings on the use of ARM assembler 1, 2

MNF Floating point instructions 1, 2

MOD Expressions and operators

modes The ARM CPU 1, 2, 3, Exception handling 1, 2

changing The ARM CPU, CPU instruction set 1, 2, Warnings on the use of ARM assembler

flags The ARM CPU 1, 2

privileged The ARM CPUsee privileged modes

see also mode names The ARM CPU

modules ObjAsm, The ARM CPU, Writing relocatable modules 1, 2

MOV CPU instruction set 1, 2, 3, 4

MRC CPU instruction set 1, 2

MRS CPU instruction set 1, 2

MSR CPU instruction set 1, 2

MUF Floating point instructions 1, 2

MUL CPU instruction set 1, 2, Warnings on the use of ARM assembler 1, 2, 3

multiplication Example assembler fragments 1, 2, 3

see also Example assembler fragments instructions (multiplies)

multiplier The ARM CPU 1, 2

MVF Floating point instructions 1, 2

MVN CPU instruction set 1, 2, 3, 4

Negative flag The ARM CPUsee N flag

NOFP Floating point instructions, Directives

NOINIT ARM assembly language

no op Warnings on the use of ARM assembler 1, 2

NOT Expressions and operators

NRM Floating point instructions 1, 2

numbers see constants

Auto run ObjAsm

Auto save ObjAsm

C strings ObjAsm

cacheing ObjAsm

command line ObjAsm 1, 2, 3

Command line (menu option) ObjAsm

CPU ObjAsm

Cross reference ObjAsm

Debug ObjAsm

Define ObjAsm

Display ObjAsm

Errors to file ObjAsm

Help ObjAsm

icon bar menu ObjAsm

Include ObjAsm

Length ObjAsm

Listing ObjAsm

MaxCache ObjAsm

No APCS registers ObjAsm

NoCache ObjAsm

NoTerse ObjAsm, Conditional assembly

Options ObjAsm

Others ObjAsm

output ObjAsm 1, 2

Run ObjAsm 1, 2, 3

Save options ObjAsm

SetUp dialogue box ObjAsm 1, 2, 3

SetUp menu ObjAsm

Source ObjAsm 1, 2

Suppress warnings ObjAsm

Throwback ObjAsm

Upper case ObjAsm

Width ObjAsm

Work directory ObjAsm

object files ObjAsm 1, 2, ARM assembly language, Directives

operators Expressions and operators 1, 2

addition and logical Expressions and operators

binary Symbolic capabilities 1, 2

boolean Expressions and operators

multiplicative Expressions and operators

precedence Expressions and operators 1, 2

relational Expressions and operators

shifts Expressions and operators

string manipulation Expressions and operators

unary Symbolic capabilities 1, 2

OPT Directives, Symbolic capabilities

OR Symbolic capabilities

ORG ARM assembly language, CPU instruction set, Directives, Support for AAsm source

origin Directives

ORR CPU instruction set

OS_ChangeEnvironment Exception handling

OS_ClaimProcessorVector Exception handling

output ObjAsm 1, 2

Overflow flag see V flag

PIC ARM assembly language

pipeline The ARM CPU 1, 2, CPU instruction set 1, 2, Warnings on the use of ARM assembler 1, 2

POL Floating point instructions 1, 2

POW Floating point instructions 1, 2

prefetch aborts The ARM CPU, Warnings on the use of ARM assembler

pre veneers Exception handling

PrintLib example Interworking assembler with C 1, 2

privileged modes The ARM CPU 1, 2, 3

user bank transfer CPU instruction set, Warnings on the use of ARM assembler 1, 2

processor configurations see configurations

processor modes see modes

processor status register see PSR

program counter see PC

PSR The ARM CPU 1, 2, 3, 4, CPU instruction set 1, 2, 3, 4, 5, 6, Exception handling, Warnings on the use of ARM assembler 1, 2

R14 see LR

R15 see PC and PSR

random numbers Example assembler fragments

RDF Floating point instructions 1, 2

READONLY ARM assembly language

REENTRANT ARM assembly language

registers The ARM CPU 1, 2, 3, 4, 5

bank organisation The ARM CPU 1, 2

floating point Floating point instructions

floating point control Floating point instructions 1, 2, 3

floating point status Floating point instructions 1, 2, 3

names ObjAsm 1, 2, ARM assembly language, Symbolic capabilities

see also register names The ARM CPU

REL ARM assembly language

relocatable modules see modules

repetitive assembly Macros

reserving memory see memory (reserving)

resets The ARM CPU

RFC Floating point instructions

RFS Floating point instructions

RIGHT Symbolic capabilities

RISC OS Interworking assembler with C

RLIST Directives

RMF Floating point instructions 1, 2

RN Symbolic capabilities

Rn and Rn see registers (names)

RND Floating point instructions 1, 2

ROL Expressions and operators

ROR CPU instruction set, Expressions and operators

Rotate Right see ROR

Rotate Right with Extend see RRX

rotates CPU instruction set 1, 2, 3

ROUT Symbolic capabilities

RPW Floating point instructions 1, 2

RRX CPU instruction set 1, 2

RSB CPU instruction set

RSC CPU instruction set

RSF Floating point instructions 1, 2

SBC CPU instruction set 1, 2

semaphores CPU instruction set

SET ObjAsm, ARM assembly language, Symbolic capabilities, Macros

SFM Floating point instructions 1, 2

shift types CPU instruction set 1, 2

shifts CPU instruction set 1, 2, 3

amount CPU instruction set

mnemonics CPU instruction set

SHL Symbolic capabilities

SHR Symbolic capabilities

sign extension Example assembler fragments

SIN Floating point instructions 1, 2

sl see registers (names)

SMLAL CPU instruction set 1, 2, Example assembler fragments

SMULL CPU instruction set 1, 2, Example assembler fragments

software interrupts The ARM CPU 1, 2

source files Directives

line length ARM assembly language

SP The ARM CPU

SPSR The ARM CPU 1, 2, 3, 4, CPU instruction set 1, 2

SQT Floating point instructions 1, 2

SrcEdit ObjAsm

stack pointer see SP

stack limit checkingObjAsm

stacks CPU instruction set 1, 2, Floating point instructions

STC CPU instruction set 1, 2, Warnings on the use of ARM assembler 1, 2

STF Floating point instructions 1, 2, Warnings on the use of ARM assembler

STM CPU instruction set 1, 2, Directives, Warnings on the use of ARM assembler 1, 2, 3, 4, 5

STR CPU instruction set 1, 2, Symbolic capabilities, Expressions and operators, Warnings on the use of ARM assembler

STRB see STR

strings see constants

STRONG Support for AAsm source

SUB CPU instruction set 1, 2, 3

subroutines CPU instruction set

SUBT Directives

SUF Floating point instructions 1, 2

summary ObjAsm 1, 2

Supervisor mode see SVC mode

SVC mode The ARM CPU 1, 2, 3, 4, 5, 6, 7, CPU instruction set, Writing relocatable modules

SWI CPU instruction set 1, 2, 3, Writing relocatable modules, Warnings on the use of ARM assembler

SWP CPU instruction set 1, 2, Warnings on the use of ARM assembler

symbols ObjAsm, ARM assembly language, CPU instruction set, Directives, Symbolic capabilities 1, 2

external Directives

length Expressions and operators

local Directives

TEQ The ARM CPU, CPU instruction set 1, 2, Warnings on the use of ARM assembler

TEQP see TEQ

throwback ObjAsm

titles Directives

tools ObjAsm

common features ObjAsm 1, 2

TRUE ARM assembly language, Symbolic capabilities

TST The ARM CPU, CPU instruction set 1, 2, Warnings on the use of ARM assembler

TSTP see TST

TTL Directives

typographic conventions see conventions

UMULL CPU instruction set 1, 2, Example assembler fragments

UND mode The ARM CPU 1, 2, 3

undefined instructions see instructions (undefined)

Undefined mode see UND mode

URD Floating point instructions 1, 2

User mode The ARM CPU 1, 2, 3

VAR Symbolic capabilities

variables ObjAsm 1, 2, Symbolic capabilities 1, 2

global Symbolic capabilities

local Symbolic capabilities, Macros

see also variable names

vn see registers (names)

WEAK Directives

WEND Conditional assembly, Macros

WFC Floating point instructions

WFS Floating point instructions

WHILE Conditional assembly, Macros

work directory ObjAsm

Zero flag see Z flag