www.riscos.com Technical Support: Acorn Assembler

Overview of chapters

• Assembler: Chapter 1: Introduction
• Assembler: Chapter 2: ObjAsm
• Assembler: Chapter 3: The ARM CPU
• Assembler: Chapter 4: ARM assembly language
• Assembler: Chapter 5: CPU instruction set
• Assembler: Chapter 6: Floating point instructions
• Assembler: Chapter 7: Directives
• Assembler: Chapter 8: Symbolic capabilities
• Assembler: Chapter 9: Expressions and operators
• Assembler: Chapter 10: Conditional assembly
• Assembler: Chapter 11: Macros
• Assembler: Chapter 12: Exception handling
• Assembler: Chapter 13: Writing relocatable modules
• Assembler: Chapter 14: Interworking assembler with C
• Assembler: Appendix A: Changes to the assembler
• Assembler: Appendix B: Error messages
• Assembler: Appendix C: Example assembler fragments
• Assembler: Appendix D: Warnings on the use of ARM assembler
• Assembler: Appendix E: Support for AAsm source

Assembler: Chapter 1: Introduction

• Introduction
  • Installation
  • Assembler tools
    • Objasm
  • This user guide
    • Note on program examples
  • Conventions used in this manual

Assembler: Chapter 2: ObjAsm

• ObjAsm
  • Starting ObjAsm
  • The SetUp dialogue box
    • Include
    • Options
  • The SetUp menu
    • The command line
    • Controlling syntax
    • Predefining a variable
    • Controlling cacheing
    • Handling warnings and errors
    • Listings
    • Choosing your work directory
    • Specifying other command line options
  • ObjAsm output
  • ObjAsm icon bar menu
  • Example ObjAsm session
  • ObjAsm command lines
    • Command line options available from the desktop
    • Command line options not available from the desktop

Assembler: Chapter 3: The ARM CPU

• The ARM CPU
  • Introduction
    • Bus widths
    • Instruction set
    • Pipelining
    • Memory interface
    • Data types
  • Block diagram of core
  • 26 bit architecture
    • Processor modes
    • Registers
    • Register R15
    • Register R14
    • Changing operating modes
  • 32 bit architecture
    • New features in ARM6
    • Processor configuration
    • Processor modes
      • The 26 bit processor modes
    • RISC OS processor configuration and modes
    • Registers
    • The CPSR and SPSR registers
  • Exceptions
    • Introduction
    • FIQ (Fast interrupt request)
    • IRQ (Interrupt request)
    • Address exception trap
    • Abort
      • Abort during instruction prefetch
      • Abort during data access
      • Abort during an internal cycle
      • Using aborts to implement virtual memory systems
    • Software interrupt
    • Undefined instruction trap
    • Reset
    • Vector summary
    • Exception Priorities
    • Interrupt latencies

Assembler: Chapter 4: ARM assembly language

• ARM assembly language
  • General
  • Input lines
  • AREAs
    • Area attributes
  • ORG and ABS
  • Symbols
  • Labels
  • Local labels
    • References to local labels
  • Comments
  • Constants
    • Numbers
    • Strings
    • Boolean
  • The END directive

Assembler: Chapter 5: CPU instruction set

• CPU instruction set
  • The condition field
    • Conditional instruction sequence
  • Instruction timings
  • The barrel shifter
    • Unshifted register
    • Register shifted by a constant amount
    • Value resulting from rotating register and carry bit one bit right
    • Register shifted by n bits
    • 8-bit constant rotated right by 2n bits
    • 8-bit constant rotated right by 2n bits and specified explicitly
  • Shift types
    • Mnemonics
    • Specification of the shift amount
      • Instruction specified shift amount
      • Register specified shift amount
    • Logical shift left, or arithmetic shift left
      • Special cases
    • Logical shift right
      • Special cases
    • Arithmetic shift right
      • Special cases
    • Rotate right
      • Special cases
    • Rotate right with extend
  • Coprocessor instructions
  • Branch, Branch with Link (B, BL)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • The link bit
    • 32 bit operation
      • Calculating the offset
      • The link bit
    • Examples
  • Data processing
    • Instruction format
    • Assembler syntax
      • MOV and MVN - single operand
      • CMN, CMP, TEQ and TST - no result written
      • ADC, ADD, AND, BIC, OR, ORR, RSB, RSC, SBC, SUB - two operands
      • Parameters
      • Opcodes
    • Synopsis
    • The S bit
      • Logical operations (AND, BIC, EOR, MOV, MVN, ORR, TEQ, TST)
      • Arithmetic operations (ADC, ADD, CMP, CMN, RSB, RSC, SBC, SUB)
    • The P flag
    • Shifts
    • Immediate operand rotates
    • Using R15 as the destination or operand
      • Using R15 as the destination
      • Using R15 as an operand
    • 32 bit operation
      • TEQP, TSTP, CMPP and CMNP
      • Using R15 as the shift register
      • Using R15 as the destination
    • Examples
  • PSR transfer (MRS, MSR)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • Operand restrictions
    • Reserved bits
    • Examples
  • Multiply and Multiply-Accumulate (MUL, MLA)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • PSR flags
    • Operand restrictions
    • 32 bit operation
    • Examples
  • Multiply Long and Multiply-Accumulate Long (UMULL, SMULL, UMLAL, SMLAL)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • PSR flags
    • Operand restrictions
    • Examples
  • Single data transfer (LDR, STR)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • Offsets and auto-indexing
    • Shifted register offset
    • Bytes and words
    • Use of R15
    • Address exceptions
    • Data Aborts
    • 32 bit operation
    • Examples
  • Block data transfer (LDM, STM)
    • Instruction format
    • Assembler syntax
      • Addressing mode names
    • Synopsis
    • The register list
    • Addressing modes
    • Transfer of R15
    • Forcing transfer of the user bank
    • Use of R15 as the base
    • Inclusion of the base in the register list
    • When the base register is in the list of registers
    • Address exceptions
    • Data Aborts
      • Aborts during STM instructions
      • Aborts during LDM instructions
    • 32 bit operation
    • Examples
  • Single data swap (SWP)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • Bytes and words
    • Use of R15
    • Data aborts
    • Examples
  • Software interrupt (SWI)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • Return from the supervisor
    • Comment field
    • 32 bit operation
    • Examples
  • Coprocessor data operations (CDP)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • The coprocessor fields
    • Restriction
    • Examples
  • Coprocessor data transfers (LDC, STC)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • The coprocessor fields
    • Addressing modes
    • Address alignment
    • Use of R15
    • Address exceptions
    • Data aborts
    • 32 bit operation
    • Examples
  • Coprocessor register transfers (MCR, MRC)
    • Instruction format
    • Assembler syntax
    • Synopsis
    • The coprocessor fields
    • Transfers to R15
    • Transfers from R15
    • 32 bit operation
      • Transfers to R15
      • Transfers from R15
    • Examples
  • Undefined instructions
    • Instruction format
    • Assembler syntax
    • Synopsis
  • Instruction set summary
    • Instruction formats
    • Assembler syntax
      • Parameters for the above, alphabetically sorted
    • Synopsis
  • Further instructions
    • Extended range immediate constants
      • Synopsis
    • The ADR instruction
      • Assembler syntax
      • Synopsis
        • Register-relative
        • Program-relative
        • Numeric
    • The ADRL instruction
      • Assembler syntax
      • Synopsis
    • Literals
      • Assembler syntax
      • Synopsis

Assembler: Chapter 6: Floating point instructions

• Floating point instructions
  • Programmer's model
  • Available systems
  • Precision
  • Floating point number formats
    • IEEE Single Precision (S)
    • IEEE Double Precision (D)
    • Double Extended Precision (E)
    • Packed Decimal (P)
    • Expanded Packed Decimal (EP)
  • Floating point status register
    • System ID byte
    • Exception Trap Enable Byte
    • System Control Byte
      • ND - No denormalised numbers bit
      • NE - NaN exception bit
      • SO - Select synchronous operation of FPA
      • EP - Use expanded packed decimal format
      • AC - Use alternative definition for C flag on compare operations
    • Cumulative Exception Flags Byte
      • IVO - invalid operation
      • DVZ - division by zero
      • OFL - overflow
      • UFL - underflow
      • INX - inexact
  • Floating Point Control Register
    • The FPPC system
    • The FPA system
  • Assembler directives and syntax
    • Floating point number input
    • NOFP directive
    • Floating point register equating: FN
    • Floating point store loading directives
  • The instruction set
    • Floating point coprocessor data transfer
      • Floating point literals
    • Floating point coprocessor multiple data transfer
    • Floating point coprocessor register transfer
    • Floating point coprocessor data operations
    • Floating point coprocessor status transfer
  • Finding out more...

Assembler: Chapter 7: Directives

• Directives
  • Storage reservation and initialisation - DCB, DCW and DCD
  • Floating point store initialisation - DCFS and DCFD
  • Describing the layout of store - ^ and #
  • Organisational directives - END, ORG, LTORG and KEEP
  • Links to other object files - IMPORT and EXPORT
  • Links to other source files - GET/INCLUDE
  • Diagnostic generation - ASSERT and !
  • Dynamic listing options - OPT
  • Titles - TTL and SUBT
  • Miscellaneous directives - ALIGN, NOFP, RLIST and ENTRY

Assembler: Chapter 8: Symbolic capabilities

• Symbolic capabilities
  • Setting constants
  • Local and global variables - GBL, LCL and SET
  • Variable substitution - $
  • Built-in variables

Assembler: Chapter 9: Expressions and operators

• Expressions and operators
  • Unary operators
  • Binary operators
    • Multiplicative operators
    • String manipulation operators
    • Shift operators
    • Addition and logical operators
    • Relational operators
    • Boolean operators

Assembler: Chapter 10: Conditional assembly

• Conditional and repetitive assembly
  • Conditional assembly
    • Simple use of the IF and ENDIF directives
  • Simple use of the IF, ELSE and ENDIF directives
  • Conditional assembly and the NoTerse option
  • An example
• Repetitive assembly

Assembler: Chapter 11: Macros

• Macros
  • Syntax
  • Local variables
  • MEXIT directive
  • Default values
  • Macro substitution method
  • Nesting macros
  • A division macro

Assembler: Chapter 12: Exception handling

• Exception handling
  • RISC OS processor configuration and modes
  • The pre-veneers
    • Entering 32 bit modes
  • Claiming the hardware vectors
  • Writing to the FIQ vector

Assembler: Chapter 13: Writing relocatable modules

• Writing relocatable modules in assembler
  • Assembler directives
  • Example

Assembler: Chapter 14: Interworking assembler with C

• Interworking assembler with C
  • Examples
    • PrintLib
      • Compiling the CTestPrLib example
      • Compiling and linking CTestPrLib in separate stages
    • CStatics

Assembler: Appendix A: Changes to the assembler

• Changes to the assembler

Assembler: Appendix B: Error messages

• Error messages

Assembler: Appendix C: Example assembler fragments

• Example assembler fragments
  • Using the conditional instructions
    • Using conditionals for logical OR
    • Absolute value
    • Combining discrete and range tests
    • Division and remainder
  • Pseudo-random binary sequence generator
  • Multiplication by a constant
    • Multiplication by 2n (1,2,4,8,16,32...)
    • Multiplication by 2n+1 (3,5,9,17...)
    • Multiplication by 2n-1 (3,7,15...)
    • Multiplication by 6
    • Multiply by 10 and add in extra number
    • General recursive method for Rb := Ra×C, C a constant
  • Loading a word from an unknown alignment
  • Sign/zero extension of a half word
  • Return setting condition codes
  • Full multiply

Assembler: Appendix D: Warnings on the use of ARM assembler

• Warnings on the use of ARM assembler
  • Restrictions to the ARM instruction set
  • Instructions and code sequences to avoid
    • TSTP/TEQP/CMPP/CMNP: Changing mode
    • LDM/STM: Forcing transfer of the user bank (Part 1)
    • LDM: Forcing transfer of the user bank (Part 2)
    • SWI/Undefined Instruction trap interaction
    • Undefined instruction/Prefetch abort trap interaction
    • Single instructions to avoid
      • Any instruction that uses the 1111 condition code
      • Data processing
      • Multiply and multiply-accumulate
      • Single data transfer
      • Block data transfer
      • Single data swap
      • Coprocessor data transfers
      • Undefined instructions
      • Register access after an in-line mode change
      • Register access after an LDM that forces user mode data transfer
    • Other points to note
      • Use of R15
      • STM: Inclusion of the base in the register list
      • MUL/MLA: Register restrictions
      • LDM/STM: Address Exceptions
      • LDC/STC: Address Exceptions
      • LDC: Data transfers to a coprocessor fetch more data than expected
  • Static ARM problems
    • Case 1: LDR Rd,[PC,#expression]!
    • Case 2: LDR Rd,[PC],#expression

Assembler: Appendix E: Support for AAsm source

• Support for AAsm source
  • The -ABSolute option