www.riscos.com Technical Support:
Programmer's Reference Manual


ARM hardware

Introduction and Overview

The ARM architecture changed significantly with the introduction of the ARM6 series. The section below describes the differences in behaviour of more recent ARM processors, used with RISC OS 3.5 and later. For details of earlier ARM processors, see the chapter entitled ARM Hardware.

32 bit architecture

New features in ARM6

The most notable change made in the ARM6 series was to extend the address bus and program counter to a full 32 bits. As a result:

  • The PSR had to be separated from the PC into its own register, the CPSR (Current Program Status Register).
  • The PSR can no longer be saved with the PC when changing processor modes; instead, each privileged mode now has an extra register - the SPSR (Saved Program Status Register) - to hold the previous mode's PSR.
  • Instructions have been added to use these new status registers.

A further change was the addition of extra privileged processor modes, allowed by the PSR now having a full 32 bits to use. These modes are used to handle Undefined instruction and Abort exceptions. Consequently:

  • Undefined instructions, aborts, and supervisor code no longer have to share the same mode. This has removed restrictions on Supervisor mode programs which existed on earlier ARMs.
Processor configuration

The availability of these features in the ARM6 series (and other later compatible chips) is set by one of several on-chip control registers. One of three processor configurations can be selected:

  • 26 bit program and data space. This configuration forces ARM to operate with a 26 bit address space. In this configuration only the four 26 bit modes are available (see Processor modes below); it is impossible to select a 32 bit mode.
  • 26 bit program space and 32 bit data space. This is the same as the 26 bit program and data space configuration, except that address exceptions are disabled to allow data transfer operations to access the full 32 bit address space.
  • 32 bit program and data space. This configuration extends the address space to 32 bits, and introduces major changes to the programmer's model. In this configuration you can select any of the 26 bit and the 32 bit processor modes (see Processor modes below).
Processor modes

When configured for a 32 bit program and data space, the ARM6 and ARM7 series support ten overlapping processor modes of operation:

  • User mode: the normal program execution state - or
  • FIQ mode: designed to support a data transfer or channel process - or
  • IRQ mode: used for general purpose interrupt handling - or
  • SVC mode: a protected mode for the operating system - or
  • Abort mode (abbreviated to ABT mode): entered after a data or instruction prefetch abort
  • Undefined mode (abbreviated to UND mode): entered when an undefined instruction is executed.

The distinction between processor modes and configurations is important, and will be rigidly adhered to in the rest of this manual.

The 26 bit processor modes

When in a 26 bit processor mode, the programmer's model reverts to that of earlier 26 bit ARM processors. The behaviour is the same as that of the ARM2aS macrocell with the following alterations:

  • Address exceptions are only generated by ARM when it is configured for 26 bit program and data space.
  • The new instructions to transfer data between general registers and the program status registers remain operative. The new instructions can be used by the operating system to return to a 32 bit mode after calling a binary containing code written for a 26 bit ARM.
  • When in a 32 bit program and data space configuration, all exceptions (including Undefined Instruction and Software Interrupt) return the processor to a 32 bit mode, so the operating system must be modified to handle them.
  • If the processor attempts to write to a location between &0 and &1F inclusive (i.e. the exception vectors), hardware prevents the write operation and generates a data abort. This allows the operating system to intercept all changes to the exception vectors and redirect the vector to some veneer code. The veneer code should place the processor in a 26 bit mode before calling the 26 bit exception handler.

In all other respects, when operating in a 26 bit mode the ARM behaves as like a 26 bit ARM. (See the chapter entitled ARM Hardware.) The relevant bits of the CPSR appear to be incorporated back into R15 to form the PC/PSR with the I and F bits in bits 27 and 26. The instruction set behaves like that of the ARM2aS macrocell, with the addition of the MRS and MSR instructions.

RISC OS processor configuration and modes

Early in its startup code, RISC OS writes to the ARM's control register to change it into the 32 bit program and data space configuration, where it remains. You must not alter the processor's configuration yourself when writing code for RISC OS.

Although RISC OS runs under a 32 bit configuration, it remains in 26 bit modes for normal operation, providing a high degree of backward compatibility with code written to run on earlier 26 bit processors.

However, because the processor is in a 32 bit configuration, all exceptions (including Undefined Instruction and Software Interrupt) force the processor to a privileged 32 bit mode appropriate to the exception. There are therefore some differences in exception handling between 26 and 32 bit architecture ARM chips, although RISC OS provides a considerable degree of backward compatibility by faking 26 bit behaviour on 32 bit architecture chips in most circumstances. For full details, see the chapter entitled Hardware vectors.


The registers available in the ARM6 and ARM7 series are:

User and User26 mode SVC and SVC26 mode IRQ and IRQ26 mode ABT mode UND mode FIQ and FIQ26 mode
R8 R8_fiq
R9 R9_fiq
R10 R10_fiq
R11 R11_fiq
R12 R12_fiq
R13 R13_svc R13_irq R13_abt R13_und R13_fiq
R14 R14_svc R14_irq R14_abt R14_und R14_fiq
R15 (PC)
SPSR_svc SPSR_irq SPSR_abt SPSR_und SPSR_fiq

32 bit register organisation

These are similar to those available in the ARM2 and ARM3 series registers. The key differences are:

  • the PC is a full 32 bits wide
  • the PSR is held in its own register, the CPSR (see the chapter entitled The CPSR and SPSR registers below)
  • each privileged mode has a private SPSR register in which to save the CPSR
  • there are two new privileged modes, each of which has private copies of R13 and R14.
The CPSR and SPSR registers

The allocation of the bits within the CPSR (and the SPSR registers to which it is saved) is shown below.

The Current Process Status Register (CPSR)

Block diagram of core

ARM Core block diagram

This edition Copyright © 3QD Developments Ltd 2015
Last Edit: Tue,03 Nov 2015