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Memory
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OS Memory

OS_Memory calls have been updated. The following lists the reason codes which are allocated :

OS_Memory 0 General block operations

See PRM 5a-62

OS_Memory 1-5 Reserved for internal use

See PRM 5a-64

OS_Memory 6 Read size of physical memory arrangement tabl

See PRM 5a-65 and this section

OS_Memory 7 Read physical memory arrangement table

See PRM 5a-66 and this section

OS_Memory 8 Read memory amounts

See PRM 5a-68 and this section

OS_Memory 9 Read controller presence and logical base address

See PRM 5a-69 and this section

OS_Memory 10 Lock free pool

See this section

OS_Memory 11 Map PCI memory

See this section

OS_Memory 12 Recommend page

See this section

OS_Memory 13-23 Reserved for future expansion
OS_Memory 24 Check memory access

See this section

OS_Memory 25 Read controller presence and physical base address

See this section

OS_Memory 6 (Read size of physical memory arrangement table)
On entry
   R0 = 6 (reason code), all flag bits are currently reserved and must be 0
On exit
   R1 = table size R2 = page size

This SWI is now deprecated.

OS_Memory 7 (Read physical memory arrangement table)
On entry
   R0 = 7 (reason code), all flag bits are currently reserved and must be 0
   R1 = pointer to table to fill in

This SWI is now deprecated and may not return reliable information for a given OS version.

OS_Memory 8 (Read amount of memory)
On entry
   R0 = 8 + flags:
                 bits 8-11: type of memory:
                              1 = DRAM
                              2 = VRAM
                              3 = ROM
                              4 = I/O
                              5 = Softload ROM
                              Others reserved
                 bits 12-31 reserved, must be 0

This SWI is used to read the amount of various types of memory available within the machine. On modern versions of RISC OS, the amount of VRAM will be returned as 0, as VRAM is now reserved to the video driver, rather than the Kernel. The new type 5 for softload RAM indicates the amount of memory allocated from DRAM (and excluded from the value returned for type 1).

OS_Memory 9 (Read controller presence and base logical address)
On entry
   R0 = 9 (reason code), all flag bits are currently reserved and must be 0
   R1 = controller ID:
         bits 0-7  = controller sequence number
         bits 8-31 = controller type:
                     0 = EASI card access speed control
                             1 = EASI space
                     2 = VIDC1
                     3 = VIDC20
                     Others = reserved
On exit
   R0 preserved
   R1 = controller physical address

This SWI is used to read the base address of a controller in logical address space. Under modern versions of the OS the correct way to obtain access to a controller is to create a dynamic area with the controller address mapped in to it. The Kernel will not map parts of hardware memory in future versions. This SWI is thus less useful in modern OS versions. Its behaviour has been been changed slightly to correct an oversight in the original design. The original definition stated that 0 could be returned for an absent controller, in addition to an error being reported for an invalid controller. The implementation now returns an error for all controllers which do not exist, and 0 will not be returned.

See PRM 5a-69 for the original definition.

OS_Memory 10 (Lock free pool)
On entry
   R0 = 10 + flags:
         bit 8 = call made by Wimp
         bits 9-31 reserved, must be 0

This SWI was allocated in RISC OS 4 for locking the free pool in order to implement Wimp_ClaimFreeMemory. The Wimp_ClaimFreeMemory call should not be used and this call is no longer used.

OS_Memory 11 (Map PCI memory)
On entry
   R0 = 11 + flags:
         bit 8 = set to read information, clear to map PCI space
         bits 9-31 reserved, must be 0
   R1-R3 dependent on flags

This SWI was allocated in RISC OS 4 for mapping PCI memory within the Phoebe hardware. PCI memory allocation should now be performed by clients through the PCI manager module. The PCI manager module will use physical memory areas to provide drivers with memory mappings. This call is no longer used.

OS_Memory 12 (Recommend page)
On entry
   R0 = 12 + flags :
         bit 8 = set if pages should be in DMA-able memory
         bits 9-31 reserved, must be 0
   R1 = size of contiguous region of physical memory required in bytes
   R2 = log base 2 of required alignment of base of region within physical memory, between 12 (4K) and 30 (2G).
On exit
   R3 = page number of first page which fulfills the requirements specified

This SWI is used to recommend pages of physical RAM which are unallocated and may be used for a new dynamic area. It is expected that they will be used to create a dynamic area, or to extend an existing area. An error will be returned if no pages match the required criteria. Prior to Kernel 8.77, bit 8 was not supported. This SWI call is available from RISC OS 4 onward.

OS_Memory 13-23 (reserved)
On entry
   R0 = 13 to 23

These SWI calls are reserved.

OS_Memory 24 (Check memory access)
On entry 
   R0 = 24 (reason code), all flag bits are currently reserved and must be 0
   R1 = low address
   R2 = high address
On exit
   R1 = access flags:
         bit 0 = Range is completely readable in user mode
         bit 1 = Range is completely writable in user mode
         bit 2 = Range is completely readable in privileged modes
         bit 3 = Range is completely writable in privileged modes
         bit 4 = Range is partially readable in user mode
         bit 5 = Range is partially writable in user mode
         bit 6 = Range is partially readable in privileged modes
         bit 7 = Range is partially writable in privileged modes
         bit 8 = Range is completely physically mapped
         bit 9 = Range is completely abortable (aborts handled by code)
         bit 10 = Reserved for future expansion
         bit 11 = Reserved for future expansion
         bit 12 = Range is partially physically mapped
         bit 13 = Range is partially abortable (aborts handled by code)
         bit 14 = Reserved for future expansion
         bit 15 = Reserved for future expansion
         bits 16-31 = Reserved for future expansion

This SWI is used to determine the accessibility of a range of memory. It is similar to the OS_ValidateAddress call in that it uses the Dynamic Area details to determine the availability of memory areas. The region from 'low address' to 'high address'-1 will be considered.

The flags returned indicate the access which is available for the range. Because the range may span (multiple) page boundaries the access for the range may vary across its length. Consequently, the two extents of accessibility are returned. Bits are separated into pairs of 4 bits. The lower 4 bits indicate the lowest level of accessibility for the region specified. The upper 4 bits indicate the highest level of accessibility for the region specified. If the bit sets are identical then the accessibility of the region does not change.

OS_Memory 25 (Read controller presence and base physical address)
On entry
   R0 = 25 (reason code), all flag bits are currently reserved and must be 0
   R1 = controller ID:
         bits 0-7  = controller sequence number
         bits 8-31 = controller type:
               0 = EASI card access speed control
               1 = EASI space
               2 = VIDC1
               3 = VIDC20
               4 = Reserved for Pace OS variants
               5 = Expansion ROMs
               6-31 = Reserved for Pace OS variants
               32 = Primary ROM
               33 = IOMD
               34 = FDC37C665 or similar
               Others = Reserved for future hardware
On exit
   R0 preserved
   R1 = controller physical address

This call checks for the presence of a given controller and returns its physical address. This allows hardware drivers to provide support for specific controllers which are may exist at different physical locations on other hardware. This call is similar to OS_Memory 9.

This documentation is copyright 3QD Developments Ltd 2013 and may not be reproduced or published in any form without the copyright holders permission. RISC OS is subject to continuous development and improvement as such all information is reproduced by 3QD Developments Ltd in good faith and is believed to be correct at the time of publication E&OE. 3QD Developments Ltd cannot accept any liability for any loss or damage arising from the use of any information provided as part of the RISC OS Documentation.

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