RISC OS Documentation - Environment handlers

Core

Environment handlers

The environment handlers have changed in subtle ways in order to support the 32bit operating system, and to provide necessary features for the advancement of the operating system. Each handler is dealt with separately in the following sections.

Memory limit (0)

This 'handler' is unchanged in meaning. It may return larger values where application space is larger than it has been previously.

Undefined instruction (1)

This handler is unchanged, with the exception that it is entered in SVC32 or SVC26 dependent on the operating system. See the exception registers for details of the register block changes. The handler will be entered with R14 set to PC+4 at the time of the abort.

Prefetch abort (2)

Data abort (3)

The registered Data abort handler will be called for all unhandled aborts. Aborts which may be handled by the system (including extension modules) are those generated by events such as screen cache cleaning, AbortTrapping (see separate document), and 'lazy task swapping'. Under earlier versions of the operating system, attempts to write to the system vectors (&0-&20) would result in the default abort handler, not the registered abort handler being called. This special case has been removed and the registered abort handler is now called for that range.

Address exception (4)

This handler has been removed. Attempts to modify it will be ignored and the handler will never be called. 'Address exception' has an undefined entry conditions and semantics under modern ARM processors and as such the support within the operating system has been withdrawn.

Other exceptions (5)

This handler remains unsupported.

Error (6)

This handler is unchanged, with the exception that it is entered in USR32 or USR26 dependent on the operating system.

Callback (7)

This handler is unchanged, with the exception that it is entered in SVC32 or SVC26 dependent on the operating system. The callback register block has been extended, in a similar manner to the exception register block, by adding an entry at the end for the PSR. This means that callback handlers should be aware that 17 words are now required for the block, rather than 16. Under 26bit systems the PSR entry will never be modified.

Breakpoint (8)

This handler is unchanged, with the exception that it is entered in USR32 or USR26 dependent on the operating system. The breakpoint register block has been extended in a similar manner to the exception register block by adding an entry at the end for the PSR. This means that breakpoint handlers should be aware that 17 words are now required for the block rather than 16. Under 26bit systems the PSR entry will never be modified.

Escape (9)

This handler is unchanged, with the exception that it is entered in SVC32 or SVC26 dependent on the operating system. The PRMs are unclear (PRM 1-290) about of the meaning of the value in R11 on entry. If bit 6 is set on R11, then an escape event has been requested. This may be subsequently acknowledged by other parts of the system by the handler being called with bit 6 clear. Handlers should remove any processing they have scheduled, or make such processing benign if the event is subsequently cleared. Clients should generally not raise an error immediately. The escape event is delivered under interrupts and calling OS_GenerateError or dropping to user mode to handle the event may adversely affect interrupt-based components.

Event (10)

This handler is unchanged, with the exception that it is entered in SVC32 or SVC26 dependent on the operating system. It may be removed in the near future.

Exit (11)

This handler is unchanged, with the exception that it is entered in USR32 or USR26 dependent on the operating system.

Unused SWI (12)

This handler has been removed. Attempts to modify it will be ignored and the handler will never be called. The default handler would previously call the Unknown SWI vector. This is now the only behaviour. Applications should not be expected to provide unknown SWI support. This is a legacy Arthur interface which has now been removed entirely.

Exception registers (13)

The exception registers block is now 17 words long, with the 17th word being assigned to the PSR at the time of the abort. It is not used under 26bit systems. The 3 exception handlers (Data Abort, Undefined Instruction, Prefetch abort) should be aware of this. The registers have been pre-compensated for offsets to PC. As such, the value in R15 will contain the address at which the exception occurred, rather than the address +8 or +12.

Application space (14)

This 'handler' is unchanged in meaning. It may return larger values where application space is larger than it has been previously.

Currently active object (15)

This 'handler' is unchanged in meaning. It only has any meaning within the context of an application. The definition of this value may be tightened up in future specifications.

Upcall (16)

This handler is unchanged, with the exception that it is entered in SVC32 or SVC26 dependent on the operating system.

Backward compatibility (17)

This 'handler' is reserved in order to maintain backward compatibility with other systems. Earlier versions of RISC OS have a fault which will cause an abort if this handler is accessed (either for read or write operations). This fault has been addressed in Kernel 10.24, however it is necessary for backward compatibility to avoid the use of this handler.

This documentation is copyright 3QD Developments Ltd 2013 and may not be reproduced or published in any form without the copyright holders permission. RISC OS is subject to continuous development and improvement as such all information is reproduced by 3QD Developments Ltd in good faith and is believed to be correct at the time of publication E&OE. 3QD Developments Ltd cannot accept any liability for any loss or damage arising from the use of any information provided as part of the RISC OS Documentation.

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