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This chapter describes some minor changes that do not belong in any of the previous chapters about the kernel.
A SWI has been added in RISC OS 3.5 to reset the computer. It is described overleaf.
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Does not exit!
Interrupt state is not defined
Fast interrupts are enabled
Processor is in SVC mode
Irrelevant
This call performs a hard reset.
It is only available from RISC OS 3.5 onwards.
None
None