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Programmer's Reference Manual


Appendix A: Warnings on the use of ARM assembler

Early versions of ARM 7 series processors corrupt the cache when code performs a store multiple to the last word in a cache line, which is in the cache, but is not written through the write buffer. These processors are fitted only to a very few Acorn computers.

To work round this problem, all areas of memory that can be cached must also use the write buffer. This requires that:

  • All page tables that mark pages/sections as cacheable must also mark them as bufferable.
  • The control register must never be set up such that the cache is on, but the write buffer is disabled.
  • When the cache is disabled it is also flushed (as advised in the ARM710 datasheet).

You must ensure that your own code follows these guidelines.

RISC OS does not contravene these guidelines, except for versions of ROMPatch supplied with RISC OS 3.5, a fixed version of which has been supplied with the very few processor upgrades that may show this fault.

This edition Copyright © 3QD Developments Ltd 2015
Last Edit: Tue,03 Nov 2015